The present invention relates in general to digital circuits using clocked flip-flops, and in particular to a circuit that provides a programmable clock-to-output delay time (t.sub.co).
Flip-flops are often used to synchronize incoming data to a particular clock signal. A master-slave flip-flop is a level-triggered circuit that consists of two latches. A first latch (master) accepts the input data on one clock transition and transfers this data to a second latch (slave) on the alternate clock transition.
Clock-to-output delay time (t.sub.co) is a parameter used to measure the time it takes data to propagate through a flip-flop after a clock transition. Typically, t.sub.co includes three delay components: the delay from the clock input pin to the flip-flop, the delay associated with the transfer of data from the master to the slave stage, and the delay due to transfer of data from the slave stage to the output pin. Depending on the clock frequency, very fast flip-flops can be designed with delays in the range of a few nanoseconds. However, at higher clock frequencies the noise generated by transistor switching increases. The amount of noise substantially increases, for example, in circuits where a large number of flip-flops are clocked simultaneously at these higher frequencies. To decrease noise, it is therefore sometimes desirable to have the option of running the circuit at lower clock frequencies. However, once, for example, a master-slave flip--flop is designed to operate at a typical frequency, the range of frequencies in which it can operate is limited.
It is therefore, desirable to design flip-flops that can be programmed to operate at appreciably higher frequencies than their normal operating frequency.